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24AA512/24LC512/24FC512
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
A0
A1
(NC)
A2
V SS
SDA
SCL
(NC)
WP
V CC
PDIP
1
2
—
3
4
5
6
—
7
8
SOIC
1
2
—
3
4
5
6
—
7
8
SOIJ
1
2
—
3
4
5
6
—
7
8
TSSOP
1
2
—
3
4
5
6
—
7
8
14-lead
TSSOP
1
2
3, 4, 5
6
7
8
9
10, 11, 12
13
14
DFN
1
2
—
3
4
5
6
—
7
8
CS
3
2
—
5
8
6
7
—
4
1
Function
User Configured Chip Select
User Configured Chip Select
Not Connected
User Configured Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.7V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+1.7V to 5.5V (24FC512)
2.1
A0, A1 and A2 Chip Address
2.3
Serial Clock (SCL)
Inputs
The A0, A1 and A2 inputs are used by the 24XX512 for
This input is used to synchronize the data transfer from
and to the device.
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
2.4
Write-Protect (WP)
slave address. The chip is selected if the compare is
true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V CC or V SS .
This pin must be connected to either V SS or V CC . If tied
to V SS , write operations are enabled. If tied to V CC ,
write operations are inhibited but read operations are
not affected.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘ 0 ’ or logic ‘ 1 ’. For
3.0
FUNCTIONAL DESCRIPTION
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘ 0 ’ or logic
‘ 1 ’ before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V CC (typical 10 k ? for 100 kHz, 2 k ?? for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
DS21754M-page 6
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
master device determines which mode is activated.
? 2010 Microchip Technology Inc.
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